library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX2 is
   port( sel   :  IN    std_logic;
         A, B  :  IN    std_logic;
         output:  OUT   std_logic );
end MUX2;

architecture structural of MUX2 is
   signal s1, s2  :     std_logic;
begin
   s1 <= A nand ( not sel );
   s2 <= B nand sel;
   output <= s1 nand s2;
end structural;


